1. Field of the Invention
The present invention relates to a method and a circuit for timing pulse generation, and in particular to a method and a circuit for hitless timing pulse generation which manually switch frame pulses or reference timing pulses of a working system and a protection system and to prevent errors from arising upon generation of read timing pulses or master timing pulses respectively.
2. Description of the Related Art
In recent communication devices, a high quality of transmitting signals is required, and signals with large capacity have been processed, together with a high integration of the communication devices, whereby generated timing pulses are extremely influenced by a signal switchover operation between a working system and a protection system. Therefore, a demand for generation of error-free timing pulses without any instantaneous interruption has been growing when the switchover is manually executed for maintenance or the like.
When an arrangement of operating the communication devices according to a frame pulse or a reference timing pulse that is a base of the frame pulse is adopted, and when a unit is switched over between the working system and the protection system by a manual switchover within the communication devices, a switchover between main signal data or the reference timing pulses has been required so far.
FIG. 7 shows an arrangement of a general main signal data switching circuit, in which a frame pulse FP (WK) indicating a head position of a signal and main signal data (WK) of a working system are provided to an ES (elastic store) memory 100, and a frame pulse FP (PT) and main signal data (PT) of a protection system are provided to an ES memory 200. At the ES memory 100, clock change from a received clock (WK) to a master clock MCLK is performed to the frame pulse FP (WK) and the main signal data (WK) of the working system to be transmitted to a memory RAM (WK) 500 of the working system. Similarly, at the ES memory 200, clock change from a received clock (PT) to the master clock MCLK is performed to the frame pulse FP (PT) and the main signal data (PT) of the protection system to be transmitted to a memory RAM (PT) 700 of the protection system.
A write address generator 300 of the working system generates a write address based on the frame pulse FP (WK) and the master clock MCLK. By providing this write address to the memory RAM (WK) 500, the frame pulse FP (WK) and the main signal data (WK) are written. Also, a write address generator 400 of the protection system generates the write address based on the frame pulse FP (PT) and the master clock MCLK. By providing this address to the memory RAM (PT) 700, the frame pulse FP (PT) and the main signal data (PT) are written.
A read timing pulse generation circuit 600 common to the working system and the protection system inputs the frame pulse FP (WK) of the working system and the frame pulse FP (PT) of the protection system. These frame pulses are switched by a manual switching signal SW, and a read timing pulse RTP is generated based on the master clock MCLK to be transmitted to a read address generator 800 common to the working system and the protection system.
The read address generator 800 generates a read address common to the memories RAM (WK) 500 and RAM (PT) 700 based on the read timing pulse RTP and the master clock MCLK to be provided to the memories. Then, the frame pulse FP (WK), the main signal data (WK), the frame pulse FP (PT), and the main signal data (PT) in the read address are simultaneously read out of the memories RAM (WK) 500 and RAM (PT) 700 to be respectively provided to a switch 900 simultaneously. The manual switching signal SW is provided to the switch 900, whereby the frame pulse and the main signal data according to the manual switching signal SW are selected and outputted.
FIG. 8 shows an arrangement of the read timing pulse generation circuit 600 in the above-noted main signal data switching circuit. In this arrangement, the frame pulse FP (WK) of the working system and the frame pulse FP (PT) of the protection system are provided to a selector (SEL) 1, which is switched for the selection by the manual switching signal SW. The frame pulse selected by the selector 1 is provided to one input terminal of an AND gate 2 as a window monitoring portion. When an output signal of the AND gate 2 is “H” level, the output signal is provided to an L terminal of a counter 3 as a load signal, and “0” preset to a D terminal is loaded, so that the counter 3 starts a count operation according to the master clock MCLK.
The output signal of the counter 3 is provided to a monitoring window generator (Win-DEC) 4 for generating a monitoring window, and the output signal of the monitoring window generator 4 is provided to the other input terminal of the AND gate 2 through an inverter 5. Also, the output signal of the counter 3 is decoded at a predetermined timing (frame) position by a decoder 6 and provided to a flip-flop 7. Then, the output signal is outputted as the read timing pulse RTP by the master clock MCLK.
FIGS. 9A-9H show operation time charts of the read timing pulse generation circuit shown in FIG. 8. Hereinafter, a circuit operation of FIG. 8 will now be specifically described referring to the time charts.
Firstly, supposing a frame pulse FP1 of the working system shown in FIG. 9B and a frame pulse FP2 shown in FIG. 9C are provided to the selector 1 after a power-on reset operation as shown in FIG. 9A, the selector 1 selects e.g. the frame pulse FP1 as shown in FIG. 9D with the manual switching signal SW. The selected frame pulse FP1 is transmitted to the AND gate 2. However, after the power-on reset shown in FIG. 9A, the counter 3 starts the count operation, and outputs a counter value as shown in FIG. 9E to be provided to the monitoring window generator 4 and the decoder 6 (DEC).
Supposing the monitoring window generator 4 is set to generate the monitoring window (an absorbable range of delay time difference between the frame pulses, which are fluctuations of frame pulses of both systems) which becomes “H” level in 134 bit-interval from the counter value “9652” to “66” as shown in FIG. 9F, a signal of an “L” level (corresponds to a monitoring window based on a decoded value) is provided to the AND gate 2 as a result of an inversion of a Win-DEC output at the inverter 5. Therefore, the AND gate 2 assumes a disable state, and the frame pulse FP1 after the selection is blocked by the AND gate 2, whereby no load signal is provided to the counter 3, so that the count operation is continued.
Thus, as shown in FIG. 9F, the Win-DEC output changes to the “L” level at the counter value “66”.
Supposing a fixed value “65” is set in the decoder 6 during that time, a pulse is outputted at the counter value, “65” as shown in FIG. 9G to be transmitted to the flip-flop 7, which is tapped or driven by the master clock MCLK, so that the read timing pulse RTP shifted by a single clock is generated.
The Win-DEC output from the counter value “67” to “9651” assumes “L”, and the monitoring window MW is formed from the counter value “9652” to “66”.
However, when the flame pulse after the selection shown in FIG. 9D deviates from the monitoring window MW, the AND gate 2 becomes the enable state and the load signal is provided to the counter 3. Therefore, the counter 3 loads “0” already connected to the D terminal, and the counter value returns to “0”, thereby restarting the count operation.
The same applies to frame pulses FP3 and FP4 shown in the right side of FIGS. 9C and 9D.
On the other hand, FIG. 10 shows a prior art arrangement of a master timing pulse generation circuit which is a base of the above-mentioned frame pulse. This master timing pulse generation circuit is provided in an interface card 23 (described later) as shown in FIG. 5. A reference time pulse which is a base of the generated master time pulse MTP is provided from a common portion 22 (working system or protection system) similarly shown in FIG. 5. For an arrangement of generating the master timing pulse MTP from the reference timing pulse of the working system or the protection system, the monitoring window is used in the same way as the read timing pulse generation circuit as shown in FIG. 8.
The operation of the master timing pulse generation circuit shown in FIG. 10 will now be described referring to time charts shown in FIGS. 11A-11H.
Firstly, a reference timing pulse TP (WK) of the working system and a reference timing pulse TP (PT) of the protection system respectively shown in FIGS. 11A and 11B are respectively provided to ES memories 41 and 42. At the ES memories 41 and 42, in the same way as FIG. 7, the clock change is performed from the received clocks RCK (WK) and RCK (PT) to the master clock MCLK common to the systems and outputted to the selector 1 respectively.
The manual switching signal SW shown in FIG. 11C is provided to the selector 1, which firstly selects a reference timing pulse TP1 of the working system as shown in FIG. 11D, according to the switching signal SW, to be transmitted to an AND gate 43. At this time, an input signal of the other end of the AND gate 43 is connected to a differentiation circuit 51. Since the counter value is normally “0”, no load signal is provided from the AND gate 43 to the counter 3.
Accordingly, the counter 3 starts a count from the power-on reset state, and outputs the counter value as shown in FIG. 11E in the same way as the counter value shown in FIG. 9E. The output signal of the counter 3 is decoded at the decoder 6 and a master timing pulse MTP1 as shown in FIG. 11H is outputted when the counter value is “2” in this example in the same way as the above example.
On the other hand, the output signal of the selector 1 is also provided to the AND gate 2. This AND gate 2 composes a window monitoring portion, and the counter value of the counter 3 is inputted to the other input terminal of the AND gate 2 through the monitoring window generator 4 and the inverter 5. The output signal of the AND gate 2 serves as the load signal of the counter 3 in the same way as the case of FIG. 8. It is to be noted that output signals of the AND gates 2 and 43 are provided to the counter 3 as the load signals by a logical OR circuit.
Also, an arrangement for monitoring the reception of the reference timing pulse after the clock change through the ES memories 41 and 42 at the same timing positions a predetermined times continuously is added to FIG. 10.
Namely, in the working system, the counter value of the counter 3 held by a latch circuit 44 is compared with the reference timing pulse TP (WK) outputted from the ES memory 41 at a comparison circuit 46. When both are coincident with each other, and when the coincidence is detected three times continuously at a 3-continuous protection circuit 48, the result is outputted to a selector 50. Similarly in the protection system, a latch circuit 45, a comparison circuit 47, and a 3-protection circuit 49 perform 3-continuous protection for the timing pulse TP (PT) of the protection system and the counter value of the counter 3 to be provided to the selector 50. The selector 50 selects the output signals of the 3-protection circuits 48 and 49 according to the switching signal SW. In case the pulse is received at the same timing position three times continuously at this time, the differentiation circuit 51 provides the load signal to the counter 3, so that and the counter 3 restarts counting from “0”.
On the other hand, there is a clock change circuit in which reception data are received by a received clock, at least three pieces of data with different phases are prepared from the received data by a transmission clock, one of the three pieces of the data with different phases are selected by the first and the second switchover control signals, the phases of the reception and the transmission clocks are compared with each other, the coincidence of both phases is detected, a phase fluctuation direction of the reception and the transmission clocks is monitored, and the first and the second switchover control signals for clock change are prepared based on the coincidence result of the phase comparison and the monitoring result of the phase fluctuation direction (see e.g. patent document 1).
Furthermore, there is a transmission frame method at the time of clock redundant system switchover comprising a frame synchronizing circuit for inputting a reception signal and outputting a reception frame pulse, a clock switchover circuit for receiving clocks and a clock switching signal and transmitting a selection clock, a frame phase comparison circuit for receiving the clock switching signal, the reception frame pulse, a transmission frame pulse, and the selection clock, and transmitting a frame correction control signal, and a frame generation circuit for receiving the selection clock and the frame correction control signal, and transmitting a transmission signal, and the transmission frame pulse (see e.g. patent document 2).
Furthermore, there are a device and a method for clock supply having a hold-over function for holding an output clock in a state before switching upon a clock switchover and for synchronizing the output clock to a newly selected clock after matching the phase of the selection clock with the phase of the output clock, means for comparing the phase of the newly selected clock with the phase of the held output clock at predetermined intervals, and outputting the comparison result by a digital value, and means for controlling the output clock based on the increase/decrease of the comparison result or a fixed result (see e.g. patent document 3).
[Patent Document 1]
Japanese Patent Application Laid-open No.7-336338 (FIG. 1, abstract).
[Patent Document 2]
Japanese Patent Application Laid-open No.7-303099 (FIG. 1, abstract).
[Patent Document 3]
Japanese Patent Application Laid-open No.2002-44062 (FIG. 1, abstract).
As described above, there have been disadvantageous in the read timing pulse generation circuit used for the main signal data switching circuit and the master timing pulse generation circuit for generating the master timing pulse which forms a base of the frame pulse used for the main signal data switching circuit, as follows:
(1) Problem of Read Timing Pulse Generation Circuit
As shown in the time charts shown in FIGS. 9A-9H, supposing the frame pulse FP1 shown in FIG. 9B is not normal, the monitoring window MW by the monitoring window generator 4 has the selected frame pulse FP1 around the center as a result of the selection of the frame pulse FP1 at the selector 1. Namely, as long as the frame pulse (e.g. FP1) outputted at an error position in an unstable state such as a recovery time from a fault state does not deviate from the monitoring window MW, and even though the frame pulse FP3 which then coincidentally becomes normal as shown in FIG. 9B is provided to the AND gate 2 as the frame pulse FP3 after selection as shown in FIG. 9D, the monitoring window is not regenerated, and the monitoring window continues at a position deviating from the normal position since the frame pulse FP3 exists at the margin of the monitoring window NW. As a result, a read timing pulse which is not normal is generated when the switching operation by the manual switching signal SW is performed.
(2) Problem of Master Timing Pulse Generation Circuit
In the time charts of the master timing pulse generation circuit shown in FIGS. 11A-11H, every time the working system-protection system switchover of the reference timing pulse is executed as shown in FIG. 11C, the reference timing pulses TP1, TP4, TP5, and TP6 outputted from the selector 1 as shown in FIG. 11D respectively deviate from the monitoring windows MW1-MW4. When the monitoring window MW4 falls (when the inverter output rises), the output of the selector 1 selects the reference timing pulse TP8, whereby the input of the AND gate 2 assumes “2”, and the output of the AND gate 2 assumes “H” level as shown in FIG. 11G. By this signal, as shown in FIG. 11E, the counter 3 is loaded or reset to “0”, an irregular master timing pulse MTP5 is generated at the set value (“2” in this example) of the decoder 6 after the master timing pulse MTP4 as shown in FIG. 11H, resulting in an error occurrence.